Semiconductor diode having multiple regions of different conductivities



Aug. 17, 1965 F. e. ADAM 0R DIODE HAVING MULTIPLE SEMICONDUCT REGIONS OF DIFFERENT CONDUGTIVITIES Flled March 5, 1962 4 Sheets-Sheet 1 T fiat /MPUR/TY CONCN @0075 /cc) hill/FNMA m/rz G. ADAM F. G. ADAM Aug. 17, 1965 SEMICONDUCTOR DIODE HAVING MULTIPLE REGIONS OF DIFFERENT CONDUCTIVITIES Flled March 5, 1962 4 Sheets-Sheet 2 7 Wm m 3; 2 15% N 0 m dnw 0 5 3w O O N v ii ww wnw Y 4: r n M AV 0 fie Aug. 17, 1965 F. s. ADAM 3,201,664 SEMICONDUCTOR DIODE HAVING MULTIPLE REGIONS OF DIFFERENT CONDUCTIVITIES Filed March 5, 1962 4 Sheets-Sheet 3 (9 LEAD WIRE Au/Sb 05 05/7 Au/Gcz 05/ 050" 5 LEAD W/RE M/Vmm? FR T Z G. A DA M ATTORA/EV Aug. 17, 1965 F. G. ADAM 3,201,664

SEMICONDUCTOR DIODE HAVING MULTIPLE REGIONS OF DIFFERENT CONDUCTIVITIES Filed March 5, 1962 v 4 Sheets-Sheet 4 Au/Ga DEPOS/T LEAD W/RE United States Patent 3,201,664 SEMICONDUQTOR DIODE HAVING MULTIPLE REGIONS OF DIFFERENT CQNDUCTIVITHES Fritz Gunter Adam, Aldwych, London, England, assignor to International Standard Electric Corporation, New York, N.Y., a corporation of Delaware Filed Mar. 5, 1962, Ser. No. 177,427 Claims priority, application Great Britain, Mar. 6, 1961, 8,084/61 6 Claims. (Cl. 317-434) The present invention relates to semiconductor diodes.

At the junction between the pand n-type regions of a semiconductor diode there exists a narrow intermediate region in which there are practically no free charge carriers. Accordingly, although the fixed charges of the ionised donors and acceptors compensate one another over the region as a whole, there is a net positive or negative space charge at any particular part of the intermediate region, which is therefore known as a space charge region.

In the absence of any external voltage applied to the junction the width of the space charge region depends on the composition of the pand n-regions on either side. Moreover, since it consists of a region containing no free charge carriers sandwiched between two regions containing large members of such carriers the space charge region acts in many ways like a parallel plate condenser. If a reverse bias is applied to the junction, free charge carriers are removed from those parts of the pand nregions adjacent to the space charge region, which therefore increases in width, i.e.its capacitance is decreased.

The exact relationship between the voltage across the junction and its capacitance depends on the distribution of donors and acceptors in those parts of the pand nregions in the neighbourhood of the junction.

The present invention provides a semiconductor diode having a first region of one conductivity type material and a second region of the opposite conductivity type material, the said second region containing a first, a second and a third sub-region in order of increasing distance from the junction between the first and second regions, the said second sub-region having a lower conductivity than the said first and third sub-regions, the said junction and the transitions between the sub-regions being abrupt.

By an abrupt junction or transition is meant one at which at least 50% of the change from the impurity concentration of one region or subregion to the impurity concentration of another region or sub-region occurs within a distance of less than l0 cms.

The invention will now be more particularly described with reference to the accompanying drawings, illustrating structures of two preferred embodiments, together with graphs and diagrams of characteristics.

Patented Aug. 17, 1965 the case may be. In FIG. 5, a wafer 1 of highly doped p-type silicon provides the substrate, to which there is applied, by plating or evaporating for example, a deposit 2 of a gold-gallium alloy to provide intimate ohmic contact between the lead wire 3 and the substrate 1. Any of the known appropriate techniques for affixing lead wires, such as compression bonding, may be employed here. In the embodiment illustrated in FIG. 5, the substrate is the third of three sub-regions making up the said second region, the other two being adjacent to it. The second sub-region 4 is of high purity p-type silicon which is preferably grown onto the substrate 1 by an epitaxial process. The layer 5 provides the first subregion and may be grown onto the second sub-region by a similar process, but with an appreciably greater p-type impurity content than prevails in the second sub-region. Adjacent to this first sub-region, applied by epitaxy or diffused into it, is a layer 6 which provides the said first region, and is of heavily doped n-type silicon material. A deposit 7 of a gold-antimony alloy is arranged between the lead wire 8 and the layer 6 to facilitate the provision of a good ohmic contact.

The structure shown in FIG. 6 differs from that already described with reference to FIG. 5 only by the addition of a fourth sub-region 9 between the aforementioned first region 6 and the first sub-region 5. This fourth sub-region is rather lightly doped silicon material of the same conductivity type as the other three subregions and is also preferably grown epitaxially onto the first sub-region 5.

It will be appreciated by those skilled in the art that a structure capable of achieving similar results can be obtained by using n-type doping wherever in the two preceding paragraphs p-type doping is referred to and vice versa. However, when a structure of the opposite type to that described is employed the deposits 2 and 7 will then need to be of a gold-antimony and a gold-gallium alloy, respectively.

Although mesa type structures have been employed and illustrated, a structure of the mesa type is not an essential feature of the invention.

The degrees to which the various layers of semiconductor material are doped and their thicknesses are the subject of the following more detailed theoretical description.

The manner in which the capacitance of a p-n junction varies with the bias applied across the junction can in the drawings: I

FIGS. 1 and 3 are sketches of the variation of impurity concentration with distance in two semiconductor diodes according to the present invention;

FIGS. 2 and 4 illustrate the manner in which the ca pacitance of the p-n junctions of the semiconductor diodes of FIGS. 1 and 3, respectively, varies with applied bias; and

FIGS. 5 and 6 show sections through mesa-type structures of two multilayer semiconductor devices, FIG. 5 showing a 4-1ayer structure and FIG. 6 a S-layer struc ture.

The structure shown in FIG. 5 shows a number of layers of semi-conductor material. Constituting the sub-regions referred to above, which together make up the first or second main regions of por n-type conductivity, as

be calculated in the following manner for the case of an impurity distribution varying according to the function N(x), where the x is a distance measured along an axis at right angles to the plane of the junction:

The dynamic capacitance per unit area of a space charge layer can be defined as dL dV One can therefore express Q U J Q dVB dL Where .N(x)=N (x)-N (x)=net concentration of ionised impurity atoms. Inserting (2a) into (1), we obtain for the capacity In order to derive the applied voltage V as a function of L the depletion layer width on the n-side, we make the following assumptions:

N(x) for x 0 (n-type) N(x) 0 for x 0 (p-type) Otherwise the net impurity density N(x) may be arbitrary, but integrable. As in Equation 2 we neglect throughout the contribution of the mobile carriers of the space charge. This should be a good approximation, at least as long as reverse voltages V greater than the built in voltage V are considered.

Then, for the potential V in the space charge region the Poisson equation holds in the simple form:

Integrating once gives:

f N(x)dx+A da: ke 0 Boundary conditions are:

q {for x=L (5a) 01:1; and x=L (5b) Using (5a) one finds:

A=- --f N(x)dx and f,Z=;f; No dx Inserting (5b) into (6) one obtains the overall charge neutrality condition:

1! N(x)dx=0 (7) A further integration of (6) leads to q X JL V(.E) keufo x N(x)dx da: (8)

assuming that V=0 for x=0. The total potential drop across the reversed biased junction is therefore L can be calculated from (7) as a function of L and Considering now the semiconductor diode whose variation of impurity concentration is shown in FIG. 1, this contains a first region of p-type semiconductor material having P0 acceptor atoms/cc. and a second region of n-type conductivity. The second region consists of three subregions, a first subregion of width x cms., containing N donor atoms/cc., a second subreg-ion of width (x x cms., containing N donor atoms/cc, and a third subregion containing N donor atoms/ cc. As indicated in FIG. 1, the concentration of donor atoms in the second subregion is less than the concentration of donor atoms in the first subregion.

The function N(x) for this embodiment is therefore given by:

Further, N N and N N and if P N the first region is so heavily doped than one can, according to (7 neglect L Application of Equation 13 with L =0 leads to:

The relationship between the capacitance of the junction and theapplied voltage is obtained by using these equations in conjunction with Equation 12, above. The result is shown in FIG. 2 in which c/c*, where This device has the following properties:

V =6.75 volts C (at 6.75 volts)=3530 pf/crn. AV= 0 .l6 volt C (at 6.91 volts)=706 pf./cm.

A further device made according to FIG. 1 has the following dimensions and impurity concentrations: x =ln N =l0 cm. V*=l5 volts x =1O N =1O cm. C 10,600 pf./cm.

Its properties are as follows:

V =7.5 volts C (at 7.5 volts) 10,600 pf./cm. AV=0.75 volt C (at 7.5 volts)=l0,6(l pf./cm.

Turning now to FIG. 3, this shows the variation of impurity concentration in a further semiconductor diode according to the invention. In this case the diode has a first region of p-type conductivity material containing P acceptor atoms/ cc. and a second region of n-type conductivity. With the second region are first, second, third, and fourth subregions containing N N N and N donor atoms/co, respectively, the concentration of donor atoms in the second subregion being less than the concentration in both first and third subregions. The first, second and fourth subregions have widths of (x x (x --x and x cms., respectively.

The function N(x) for this embodiment is given by:

N(:c) N for x fixszo N for $00 $10 N 3 for 222% Further, N N N N and N N and assuming that P N the first region is so heavily doped that one can, according to (7), neglect L Application of Equation 13 with L =O leads to:

As above, the relationship between the capacitance of the junction and the applied voltage is obtained by using these results and Equation 12, above. FIG. 4 shows C/C* plotted against V /V*.

As in FIG. 2 there is a certain voltage V in FIG. 4 at which the capacitance of the junction suddenly falls, by a factor of 10 or more,

In one device having an impurity distribution according to that shown in FIG. 3 the dimensions and impurity concentrations are as follows:-

( for 03L 3x AV=0.6 volts C (at 15.6 volts)=353 pf./cm.

The narrow subregions of the diodes illustrated in FIGS. 1 and 3 can be made by the process of epitaxial growth, as described above in connection with FIGS. 5 and 6.

In consideration of the choice of voltage range for the range in which the capacitance of the device is highly sensitive to changes in the applied voltage, it must of course be bourne in mind that the breakdown voltage of the device will set an upper limit to its operating range.

It is to be understood that the foregoing description of specific examples of this invention is not to be considered as a limitation on its scope.

What I claim is:

1. A semiconductor diode comprising a first region of one conductivity type material and a second region of the opposite conductivity type material, said second region comprising a first, a second and a third subregion in order of increasing distance from the junction between said first and second regions, said first region and each subregion having relatively constant predetermined impurity concentrations therein different from each adjacent subregion, said second subregion being of a lower conductivity and impurity concentration than said first and third subregions, and a pair of electrodes making low resistance connections to said first region and third subregion.

2. A semiconductor diode according to claim 1 wherein said first region is of higher conductivity than any part of said second region.

3. A semiconductor diode according to claim 1 wherein said second region further includes a fourth sub-region, said fourth subregi-on being situated between said junction and said first su'bregion and being of a lower conductivity and impurity concentration than said first subregion, and said third subregion forming the substrate for the other subregions.

4. A semiconductor diode according to claim 1 wherein said subregions in said second region are in the form of epitaxial layers.

5. A voltage variable capacitor comprising:

a semiconductor diode including a first region of one conductivity type material;

a second region, adjacent to said first region, of the opposite conductivity type material, said second region comprising a first, a second, and a third subregion in order of increasing distance from the junction between said first and second regions, said first region and each subregion having relatively constant predetermined impurity concentrations therein different from each adjacent subregion, said second subregion being of lower conductivity and impurity concentration than said first and third subregions;

a space charge region at the junction of said first and second regions;

a first electrode making low resistance connection to said first region;

a second electrode making low resistance connection to said third subregion, said electrodes forming connections to apply a reverse bias voltage across said semiconductor diode, said junction having a characteristic capacitance which decreases by a factor of 10 after application of a predetermined reverse voltage.

6. A voltage variable capacitor comprising:

a semiconductor diode including a first region of one conductivity type material;

a second region, adjacent to said first region, of the opposite conductivity type material, said second region comprising a fourth, a first, a second, and a third subregion in order of increasing distance from the junction between sai first and second regions, said first region and each said subregion having relatively constant predetermined impurity concentrations therein different from each adjacent subregion, said second and fourth subregions being of lower conductivity and impurity concentration than said first and third subregions;

a space charge region at the junction of said first and second regions;

a first electrode making low resistance connection to said first region;

a second electrode making low resistance connection to said third subregion, said electrodes forming connections to apply a reverse bias voltage across said semiconductor diode, said junction having a char acteristic capacitance which decreases by a factor of 10 after application of a predetermined reverse voltage.

(References on following page) r 7 8' I References Cited by the Examiner 3,035,213 5/62 Schmidt 31723 UNITED STATES PATENTS 3,040,219 6/62 1 14 1.5

Chri nensen et a1. 148-17g I O H REFERENCES 3/59 if f g f 3 1 5 5 IBM Disclosure Bulletin, Vol. 3, N0. 11, April 1961, 11/59 Pankove 317-235 i? J 1 f R h d D 1 1 11/59 1111111 317 234 N 388 fggg We 013mm:

9/60 'FlaIlke 148-15 u y 4/61 Shockley 317235 A 6/61 Teszner 148 1.5 10 D VID I. GALVIN, Primary Exammer.

1 Doucette et aL WINSTON A. DOUGLAS, GEORGE N. WESTBY, 7/61 GOfZbflI'geI 317 234 Examiners. 

1. A SEMICONDUCTOR DIODE COMPRISING A FIRST REGION OF ONE CONDUCTIVITY TYPE MATERIAL AND A SECOND REGION OF THE OPPOSITE CONDUCTIVITY TYPE MATERIAL, SAID SECOND REGION COMPRISING A FIRST, A SECOND AND A THIRD SUBREGION IN ORDER OF INCREASING DISTANCE FROM THE JUNCTION BETWEEN SAID FIRST AND SECOND REGIONS, SAID FIRST REGION AND EACH SUBREGION HAVING RELATIVELY CONSTANT PREDETERMINED IMPURITY CONCENTRATIONS THEREIN DIFFERENT FROM EACH ADJACENT SUBREGION, SAID SECOND SUBREGION BEING OF A LOWER CONDUCTIVITY AND IMPURITY CONCENTRATION THAN SAID FRIST AND THIRD SUBREGIONS, AND A PAIR OF ELECTRODES MAKING LOW RESISTANCE CONNECTION TO SAID FIRST REGION AND THIRD SUBREGION. 